Recently, demand for semiconductor devices has rapidly increased owing to widespread use of electronic equipment. In particular, the increasing popularity of some electronic equipment such as computers, for example, is increasing the demand for large semiconductor memories.
Early DRAMs used storage cells each consisting of three transistors and were manufactured using P type channel metal-oxide-semiconductor (PMOS) technology. Later, a DRAM storage cell structure consisting of one transistor and one capacitor was developed. In fabricating the capacitor, a contact hole is firstly patterned to form a capacitor node. Next, a polysilicon patterning is performed to form a lower plate of the capacitor.
As semiconductor memory devices becomes more highly integrated, the area occupied by a capacitor of a DRAM storage cell typically shrinks. Thus, the capacitance of the capacitor is reduced owing to its smaller electrode surface area. However, a relatively large capacitance is required to achieve a high signal-to-noise ratio in reading the memory cell and to reduce soft errors (due to alpha particle interference). Therefore, it is desirable to reduce the cell dimension and yet obtain a high capacitance, thereby achieving both high cell integration and reliable operation.
Furthermore, as semiconductor memory devices become more highly integrated, the aspect ratio of the contact holes increase, resulting in difficulties in fabricating the capacitors. Accordingly, there is a need for a method of forming a DRAM capacitor having a contact hole with a low aspect ratio and high capacitance.